Project Summary | GaN Wafer Process Optimization

Project Summary: GaN Wafer Process Optimization

Patented process for off-angle GaN substrates eliminating polishing and automating data pipelines.

GaN wafer semiconductor process optimization

Project Snapshot

Role: Process Engineer / Patent Inventor
Domain: Semiconductor manufacturing (III-V materials)
Stack: SPC, DOE, process modeling, automated data collection, patent filing
Timeline: Research through patent and production

Intellectual property

Patent EP3231006B1

Granted European patent for novel off-angle GaN substrate manufacturing process with documented innovation.

Process improvement

Eliminated Polishing Step

Process optimization removed a costly polishing step, reducing manufacturing cost and cycle time for GaN substrates.

Data automation

Automated Data Pipeline

Built automated data collection and statistical process monitoring replacing manual data handling across the wafer line.

Technical Architecture

graph TD
    subgraph Growth
        A[Wafer Growth] --> B[Metrology]
    end

    subgraph Optimization
        B --> C[DOE Optimization]
        C --> D[Process Qualification]
    end

    subgraph Automation
        D --> E[Automated Data Handling]
        E --> F[SPC Monitoring]
    end

    subgraph IP
        C --> G[Novel Process Documentation]
        G --> H[Patent Filing]
        H --> I[Patent EP3231006B1]
    end

    subgraph Production
        F --> J[Qualified Production]
        J --> K[Cost Reduction]
    end

Architecture: Wafer growth and metrology feed DOE optimization to qualify the process. Automated data handling and SPC monitoring ensure production consistency. The novel process approach was documented and filed as patent EP3231006B1.

Decision Tradeoffs

Option Considered	Pros	Cons	Decision
DOE-Based Process Optimization	Systematic, reproducible, patentable innovation	Higher upfront experimental cost with GaN substrates	Selected — systematic approach yielding patentable, reproducible results
Vendor-Recommended Parameters	Quick to implement, lower initial risk	Suboptimal for off-angle substrates, no IP value	Considered — simpler but suboptimal for novel substrate geometry
Trial-and-Error	No planning overhead	Too expensive with GaN substrates, not reproducible	Rejected — prohibitively expensive given GaN substrate costs

Problem

GaN substrate manufacturing required a costly polishing step and lacked automated data handling. The off-angle substrate process was unoptimized, driving up cost and cycle time.

Approach

Optimized the off-angle GaN wafer process to eliminate polishing using systematic DOE methodology. Automated data collection and built statistical process controls for production monitoring. Documented the novel approach in a patent filing.

Outcome

Patented process (EP3231006B1) for off-angle GaN substrates. Eliminated the polishing step, reducing cost and cycle time. Automated data pipeline enabled consistent process monitoring and quality control.

Leadership Contribution

Architecture: Designed the DOE optimization strategy for off-angle GaN substrates and the automated data collection pipeline.
Team: Coordinated with crystal growth engineers, metrology specialists, and patent attorneys to develop and protect the novel process.
Governance: Established process qualification criteria, SPC control limits, and documentation standards supporting the patent filing.
Outcomes: Secured granted patent, eliminated polishing step, and delivered automated process monitoring for production use.

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